Global dielectric and barrier layer
US9209072B2 · kind B2 · utility
2Cited by
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20Claims
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Key dates
| Filing date | Oct 25, 2013 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Oct 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating a semiconductor device are described. The method includes forming a patterned oxide layer having a plurality of openings over a substrate, depositing a metal layer in the openings to form metal plugs, depositing a global transformable (GT) layer on the oxide layer and the metal plugs, and depositing a capping layer directly on the GT layer without exposing the GT layer to ambient air. The GT layer on the oxide layer transforms into a dielectric oxide and the GT layer on the metal plugs remains conductive during deposition of the capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.