III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method
US9209095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Apr 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. Fin hardmasks are formed on the wafer. A dummy gate is formed on the wafer, over the fin hardmasks. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer and the dummy gate is removed selective to the dielectric filler layer so as to form a trench in the filler layer. Fins are patterned in the wafer using the fin hardmasks exposed within the trench, wherein the fins will serve as a base region of the bipolar transistor device. The fins are recessed in the base region. The base region is re-grown from an epitaxial SiGe, Ge or III-V semiconductor material. A contact is formed to the base region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.