Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns
US9209244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2012 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Apr 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.