Integrated circuits with memory cells and methods of manufacturing the same
US9209275B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Jul 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes removing a central plug from between a first memory cell and a second memory cell to define a center gap. Each of the first and second memory cells include a control gate with a control gate height, a cap overlying the control gate, a select gate adjacent to the control gate, and a select gate dielectric between the control gate and the select gate. The select gate is recessed to a select gate height while the cap overlies the control gate, where the select gate height is less than the control gate height. A memory spacer is formed overlying the select gate dielectric and adjacent to the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.