Inventor · Singapore, SG

Alex See

32Patents
5h-index
52Co-inventors
72Inventor score

Filing activity: Apr 24, 2000 → Jul 5, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US6204137A Method to form transistors and local interconnects using a silicon nitride dummy gate technique Electricity 24 Expired
US7892900B2 Integrated circuit system employing sacrificial spacers Electricity 7 Active
US8058123B2 Integrated circuit and method of fabrication thereof Electricity 7 Active
US8012839B2 Method for fabricating a semiconductor device having an epitaxial channel and transistor having same Electricity 6 Active
US9543502B2 Small pitch and high density contact array Electricity 5 Active
US7745320B2 Method for reducing silicide defects in integrated circuits Electricity 5 Active
US10446607B2 Integrated two-terminal device with logic device for embedded application Electricity 4 Active
US9520371B2 Planar passivation for pads Electricity 4 Active
US9287197B2 Through silicon vias Electricity 3 Active
US7776699B2 Strained channel transistor structure and method Electricity 3 Active
US8324011B2 Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing Electricity 2 Active
US9511474B2 CMP head structure with retaining ring Performing Operations; Transporting 2 Active
US9209275B1 Integrated circuits with memory cells and methods of manufacturing the same Electricity 2 Active
US9620418B2 Methods for fabricating integrated circuits with improved active regions Electricity 2 Active
US8860142B2 Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction Electricity 2 Active
US9437547B2 Through silicon vias Electricity 2 Active
US10608046B2 Integrated two-terminal device with logic device for embedded application Electricity 2 Active
US8546873B2 Integrated circuit and method of fabrication thereof Electricity 1 Active
US10410854B2 Method and device for reducing contamination for reliable bond pads Electricity 0 Active
US8293544B2 Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction Electricity 0 Active
US8716076B2 Method for fabricating a semiconductor device having an epitaxial channel and transistor having same Electricity 0 Active
US7960283B2 Method for reducing silicide defects in integrated circuits Electricity 0 Active
US10115625B2 Methods for removal of hard mask Electricity 0 Active
US9511470B2 CMP head structure with retaining ring Performing Operations; Transporting 0 Active
US9202746B2 Integrated circuits with improved gap fill dielectric and methods for fabricating same Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.