Combination ESD protection circuits and methods
US9209620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Dec 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/676
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.