Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
US9213656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2013 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Jan 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.