Memory architecture of thin film 3D array
US9214351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2013 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Dec 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.