Equal gate height control method for semiconductor device with different pattern densites
US9214358B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Oct 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor integrated circuit (IC) that has substantially equal gate heights regardless of different pattern densities in different regions of the IC includes providing a substrate with a first pattern density in a first region of the IC and a second pattern density in a second region of the IC, forming a first polysilicon layer above the substrate, the first polysilicon layer having an uneven upper surface, forming a stop layer above the first polysilicon layer, treating the stop layer to change its etch selectivity relative to the first polysilicon layer, forming a second polysilicon layer above the stop layer, removing the second polysilicon layer, the stop layer, and a top portion of the first polysilicon layer, the remaining portion of the first polysilicon layer having a planar upper surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.