Patent · US Active

Highly coupled spiral planar inductors structure at bump to compensate on die excess capacitance of differential I/O

US9214426B1 · kind B1 · utility

1Cited by

5References

20Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Siamak Fazelpour · San Diego, US
Priyatharshan Pathmanathan · Wake Forest, US
John Loffink · Austin, US

Key dates

Filing date	Jul 11, 2014
Grant date	Dec 15, 2015
Priority date	—
Expiry date	Jul 11, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10D1/20
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Methods and apparatuses for reducing excess on die capacitance. The method couples a first die pad to a first via. The method couples a second die pad to a second via. The method couples a first inductor to the first die pad and the second via. The method couples a second inductor to the second die pad and the first via.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.