Patent · US Active

Fractional frequency divider

US9214943B1 · kind B1 · utility

4Cited by

13References

5Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Akshat Gupta · Vernon, US
Simon J. Gallimore · Austin, US
Deepak Negi · Noida, IN
Garima Sharda · Ghaziabad, IN

Key dates

Filing date	Oct 16, 2014
Grant date	Dec 15, 2015
Priority date	—
Expiry date	Oct 16, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K23/68
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A fractional frequency divider counts pulses of a digital input clock signal and enables a clock gating module when a preset count is reached. The clock gating module combines the outputs of two clock gating cells that receive, respectively, the input clock signal and an inverted version of the input clock signal. Output pulses are produced on both positive and negative edges of the input clock signal. This permits generation of output clock pulses that can be set to have a spacing and width granularity of half an input clock period, giving the advantages of low jitter and fine duty cycle control.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.