Programming interface and method
US9218030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Sep 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming interface and method of operating a programming interface use a system clock input, an asynchronous reset input, and an interface control input. The method selectively controls multiplexed coupling of a source register to a destination register and the destination register to a buffer register. The multiplexed coupling of the destination register to the buffer register reduces the possibility of the buffer register being corrupted when an asynchronous reset signal is applied to the programming interface. Problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems are therefore alleviated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.