System cache with coarse grain power management
US9218040B2 · kind B2 · utility
1Cited by
9References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 27, 2012 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Oct 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and individual ways are powered down when cache activity is low. A maximum active way configuration register is set by software and determines the maximum number of ways which are permitted to be active. When searching for a cache line replacement candidate, a linear feedback shift register (LFSR) is used to select from the active ways. This ensures that each active way has an equal chance of getting picked for finding a replacement candidate when one or more of the ways are inactive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.