Multimaster serial single-ended system fault recovery
US9218247B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2013 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Jan 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system to recover a multimaster serial single-ended bus and a faulted connected device includes a director device connected to the faulted connected device via the multimaster serial single-ended bus. The director device includes a central processing unit, a field programmable gate array, and a management module in communication with the faulted connected device, the management module configured to recover the faulted connected device and the multimaster serial single-ended bus. The management module may transmit a clock pulse to the faulted connected device if the faulted connected device is holding a data line (SDA) low, transmit a stop command to the faulted connected device if the faulted connected device is holding SDA low and/or read and compare a register value in the faulted device against an expected value to determine if the faulted device and the multimaster serial single-ended bus have been recovered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.