System cache with partial write valid states
US9218286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2012 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Mar 29, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for processing partial write requests in a system cache within a memory controller. When a write request that updates a portion of a cache line misses in the system cache, the write request writes the data to the system cache without first reading the corresponding cache line from memory. The system cache includes error correction code bits which are redefined as word mask bits when a cache line is in a partial dirty state. When a read request hits on a partial dirty cache line, the partial data is written to memory using a word mask. Then, the corresponding full cache line is retrieved from memory and stored in the system cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.