Multi-core compute cache coherency with a release consistency memory ordering model
US9218289B2 · kind B2 · utility
5Cited by
7References
52Claims
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Key dates
| Filing date | Aug 2, 2013 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Jan 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/302
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.