Stack position determination in memory devices configured for stacked arrangements
US9218854B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Nov 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.