Multi-pulse programming cycle of non-volatile memory for enhanced de-trapping
US9218874B1 · kind B1 · utility
20Cited by
2References
15Claims
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Key dates
| Filing date | Aug 11, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Aug 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When writing a multi-state non-volatile memory, a de-trapping operation is included in the programming cycle. To reduce the performance penalty of including a de-trapping operation, the programming cycle of a single series of increasing pulses alternating with verify operations is replaced with a cycle including a pulse from each of two or more staircases, where each staircase is for a corresponding subset of the data states. After the multiple pulses, but before the following verify, a de-trapping operation is inserted in the programming cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.