Sidewall free CESL for enlarging ILD gap-fill window
US9218974B2 · kind B2 · utility
6Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2013 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Jun 7, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.