Patent · US Active

Structure design for 3DIC testing

US9219016B2 · kind B2 · utility

10Cited by

51References

15Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Jing-Cheng Lin · Baoshan, TW
Po-Hao Tsai · Pingzhen District, TW

Key dates

Filing date	Sep 28, 2011
Grant date	Dec 22, 2015
Priority date	—
Expiry date	May 16, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A work piece includes a first copper-containing pillar having a top surface and sidewalls, and a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar. A test pad includes a second copper-containing pillar having a top surface and sidewalls. The test pad is electrically coupled to the first copper-containing pillar. A second protection layer is disposed on the sidewalls, and not over the top surface, of the second copper-containing pillar. The first and the second protection layers include a compound of copper and a polymer, and are dielectric layers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.