Patent · US Active

Wafer-level package device having high-standoff peripheral solder bumps

US9219043B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

Maxim Integrated Products, Inc. · US

Inventors

Amit S. Kelkar · Flower Mound, US
Viren Khandekar · Flower Mound, US
Hien D. Nguyen · The Colony, US

Key dates

Filing date	Jun 28, 2013
Grant date	Dec 22, 2015
Priority date	—
Expiry date	Oct 19, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/351
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A wafer-level package device and techniques for fabricating the device are described that include a second integrated circuit chip electrically coupled to a base integrated circuit chip, where the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a base integrated circuit chip, multiple high-standoff peripheral pillars with solder bumps, and a second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-standoff peripheral pillars with solder bumps.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.