Method for polishing semiconductor wafers by means of simultaneous double-side polishing

US9221149B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Rainer Baumann · Liestal, CH
• Johannes Staudhammer · Burghausen, DE
• Alexander Heilmaier · Haiming, DE
• Leszek Mistur · Burghausen, DE
• Klaus Roettger · Bachmehring, DE

Key dates

• Filing date: Apr 10, 2014
• Grant date: Dec 29, 2015
• Expiry date: Apr 10, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/304
• WIPO field: Machine tools
• WIPO sector: Mechanical engineering

Abstract

A method of polishing a semiconductor wafer includes simultaneous double-side polishing the wafer in a gap of a polishing device between a lower polishing plate covered with a lower polishing pad and upper polishing plate covered with an upper polishing pad while supplying a polishing agent. A first of the upper and lower polishing pads is dressed using a dressing tool. The dressing tool is mounted in the gap so that it extends from the inner edge to the outer edge of the first polishing pad. The distance between the dressing tool and a second of the upper and lower polishing pads at the inner edge of the second polishing pad differs from a corresponding distance at the outer edge of the second polishing pad. After the dressing, the at least one semiconductor wafer in the gap is polished.