System and method for reducing voltage drop during automatic testing of integrated circuits

US9222974B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• V Srinivasan · Greater Noida, IN
• Satinder Singh Malhi · Noida, IN
• Tripti Gupta · Noida, IN

Key dates

• Filing date: Jan 10, 2014
• Grant date: Dec 29, 2015
• Expiry date: Feb 10, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318594
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time.