Thread-aware cache memory management
US9223709B1 · kind B1 · utility
40Cited by
4References
21Claims
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Key dates
| Filing date | Mar 1, 2013 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Oct 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache management unit manages allocation and configuration of a cache memory that is utilized by a multi-threaded processor. In some implementations, the cache management unit is configured to determine a number of active threads being executed by the multi-threaded processor, assign a separate cache unit to each active thread when the number of active threads is equal to a maximum number of active threads supported by the multi-threaded processor, and assign more than one cache unit to an active thread when the number of active threads is less than the maximum number of active threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.