Debug functionality in a secure computing environment
US9224012B2 · kind B2 · utility
3Cited by
0References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 20, 2013 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Mar 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a security processor, a first scan chain coupled to the security processor, a non-secure element, and a second scan chain coupled to the non-secure element. The computer system also includes one or more test access port controllers to control operation of the first and second scan chains, and further includes debug control logic, coupled to the one or more test access port controllers, to enable the one or more test access port controllers to activate debug functionality on the second scan chain but not the first scan chain in response to a predefined condition being satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.