General structure for computational random access memory (CRAM)
US9224447B2 · kind B2 · utility
6Cited by
2References
20Claims
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Key dates
| Filing date | Apr 23, 2014 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Apr 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1659
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cell array includes a logic connection line, a plurality of bit selection lines, and a plurality of cells. Each cell includes a memory element connected to a respective bit selection line and a logic switching element that selectively connects the memory element to the logic connection line. When logic switching elements of multiple separate cells connect their respective memory elements to the logic connection line, the memory elements connected to the logic connection line operate as a logic device with an output of the logic device stored in one of the memory elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.