Semiconductor memory device
US9224488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Dec 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes the following structure. A memory cell array includes memory cells arranged at positions where bit lines and word lines cross are arranged on a semiconductor substrate. A sense amplifier reads data stored in the memory cell. The hookup region includes a transfer transistor arranged between the memory cell array and the sense amplifier. One end of a current path of the transfer transistor is connected to a first interconnect formed between the semiconductor substrate and the bit line. The other end of the current path is connected to the sense amplifier. A guard ring region is arranged between the memory cell array and the hookup region. A contact plug is arranged to overlap the guard ring region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.