Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved gate spacer control

US9224656B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Deborah J. Riley · Sachse, US
• Seung-Chul Song · Plano, US

Key dates

• Filing date: Jul 25, 2013
• Grant date: Dec 29, 2015
• Expiry date: Jul 25, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.