Resistive memory devices
US9224945B2 · kind B2 · utility
2Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2012 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Oct 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/55
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.