Electronics device capable of efficient communication between components with asyncronous clocks
US9225343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2011 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Nov 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.