Embedded control channel for high speed serial interconnect
US9229897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2012 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Feb 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.