Simultaneous two/dual port access on 6T SRAM
US9230622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2012 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Jun 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.