Apparatuses and methods for mapping memory addresses to redundant memory
US9230692B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2013 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods related to redundant memory and mapping memory addresses to redundant memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of redundant memory sections. A programmable element block includes a plurality of programmable element sets. A programmable element set is configured to be programmed with location information for a redundant memory section of the plurality of redundant memory sections and further programmed with a respective memory address to be mapped to a redundant memory element of the redundant memory section located by the location information. A programmable element block logic is configured to associate a memory address programmed in a programmable element set with a redundant memory element of the redundant memory section located by the respective location information programmed in the programmable element set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.