Trench multilevel contact to a 3D memory array and method of making thereof
US9230905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Apr 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/845
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses. A second electrically conductive layer in the stack different from the first electrically conductive layer may be a topmost layer in a laterally central portion of a second one of the plurality of recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.