Metallization layers configured for reduced parasitic capacitance
US9230913B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Aug 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and methods to minimize parasitic capacitance in a circuit structure are provided. The structure may include a substrate supporting one or more circuits and one or more metallization layers above the substrate. The metallization layer includes a conductive pattern defined by an array of conductive fill elements, where the conductive fill elements of the array are discrete, electrically isolated elements sized to satisfy, at least in part, a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer, and to minimize parasitic capacitance within the metallization layer, as well as minimize parasitic capacitance between the metallization layer and the circuit, and if multiple metallization layers are present, between the layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.