Patent · US Active

Techniques and configurations associated with a capductor assembly

US9230944B1 · kind B1 · utility

10Cited by

0References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

William J. Lambert · Chandler, US
Michael J. Hill · Gilbert, US
Kaladhar Radhakrishnan · Chandler, US

Key dates

Filing date	Aug 20, 2014
Grant date	Jan 5, 2016
Priority date	—
Expiry date	Aug 20, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10D1/68
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor assembly may include a semiconductor wafer and a plurality of inductors disposed on a first side of the semiconductor wafer. The plurality of inductors may be embedded in electrically insulative material having a plurality of interconnect structures disposed thereon. The plurality of interconnect structures may be configured to electrically couple the plurality of inductors to a die. The IC assembly may further include a plurality of capacitors disposed on a second side of the wafer disposed opposite the first side of the wafer. The plurality of capacitors may be electrically coupled with a second plurality of interconnect structures that may be configured to electrically couple the plurality of capacitors with the die. Other embodiments may be described and/or claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.