Vertical TFT with tunnel barrier
US9230985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2014 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Oct 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/165
Abstract
A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.