Thermal-disturb mitigation in dual-deck cross-point memories
US9231202B2 · kind B2 · utility
5Cited by
6References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2013 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Jun 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.