Max Hineman
48Patents
10h-index
44Co-inventors
75Inventor score
Filing activity: Sep 1, 1995 → Dec 10, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6350679B1 | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry | Electricity | 203 | Expired |
| US6372657B1 | Method for selective etching of oxides | Electricity | 146 | Expired |
| US6358756B1 | Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme | Electricity | 90 | Expired |
| US6521931B2 | Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme | Electricity | 30 | Expired |
| US6783995B2 | Protective layers for MRAM devices | Electricity | 24 | Expired |
| US5689334A | Intracavity laser spectroscope for high sensitivity detection of contaminants | Electricity | 24 | Expired |
| US6136767A | Dilute composition cleaning method | Emerging Cross-Sectional Technologies | 23 | Expired |
| US6486108B1 | Cleaning composition useful in semiconductor integrated circuit fabrication | Chemistry; Metallurgy | 19 | Expired |
| US9299747B1 | Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques | Electricity | 15 | Active |
| US7211849B2 | Protective layers for MRAM devices | Electricity | 12 | Expired |
| US6379872B1 | Etching of anti-reflective coatings | Electricity | 10 | Expired |
| US6638843B1 | Method for forming a silicide gate stack for use in a self-aligned contact etch | Electricity | 6 | Expired |
| US6596647B2 | Dilute cleaning composition and method for using the same | Chemistry; Metallurgy | 6 | Expired |
| US9608042B2 | Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques | Electricity | 5 | Active |
| US9559146B2 | Phase-change memory cell implant for dummy array leakage reduction | Electricity | 5 | Active |
| US6844255B2 | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry | Electricity | 5 | Expired |
| US9231202B2 | Thermal-disturb mitigation in dual-deck cross-point memories | Electricity | 5 | Active |
| US7135444B2 | Cleaning composition useful in semiconductor integrated circuit fabrication | Chemistry; Metallurgy | 4 | Expired |
| US7344975B2 | Method to reduce charge buildup during high aspect ratio contact etch | Emerging Cross-Sectional Technologies | 4 | Expired |
| US6136670A | Semiconductor processing methods of forming contacts between electrically conductive materials | Electricity | 4 | Expired |
| US6313048A | Dilute cleaning composition and method for using same | Chemistry; Metallurgy | 4 | Expired |
| US6384001B2 | Dilute cleaning composition | Emerging Cross-Sectional Technologies | 4 | Expired |
| US9082714B2 | Use of etch process post wordline definition to improve data retention in a flash memory device | Electricity | 3 | Active |
| US7319071B2 | Methods for forming a metallic damascene structure | Electricity | 3 | Expired |
| US6797628B2 | Methods of forming integrated circuitry, semiconductor processing methods, and processing method of forming MRAM circuitry | Electricity | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.