Cache system for managing various cache line conditions
US9235521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2013 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | May 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.