Semiconductor device and write method
US9236123B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 24, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Sep 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.