Mitigating reliability degradation of analog memory cells during long static and erased state retention
US9236132B2 · kind B2 · utility
0Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Apr 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.