Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate
US9236474B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Feb 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.