Data reception with feedback equalization for high and low data rates
US9237041B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2015 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Jan 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method relates generally to data reception for any of a plurality of data rates. In such a method, information and phases of a clock signal are obtained by a decision feedback equalizer. The information is equalized using the phases of the clock signal with the decision feedback equalizer to provide equalized sample streams. The equalized sample streams and the phases of the clock signal are provided to a selection circuit block. A first and a second phase of the phases are swapped, along with swapping a first and a second equalized sample stream corresponding to the first phase and the second phase, responsive to a data rate of the plurality of data rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.