Memory management unit directed access to system interfaces
US9239799B2 · kind B2 · utility
3Cited by
2References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2008 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Feb 20, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.