Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode
US9240229B1 · kind B1 · utility
30Cited by
12References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2012 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Oct 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations herein involve control I/O buffer enable circuitry and/or features of saving power in standby mode. In illustrative embodiments, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.