Scheme to reduce stress of input/ output (IO) driver
US9240400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2013 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Mar 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input/output (IO) circuit is provided that reduces stress on a driver without using an additional reference voltage. The IO circuit receives an overshoot voltage and an undershoot voltage in a receive mode. The IO circuit includes a driver circuit. The driver circuit includes an NMOS transistor coupled to a PMOS transistor. A pad is coupled to the driver circuit. A PMOS protect circuit is coupled to the driver circuit and the pad. An NMOS protect circuit is coupled to the driver circuit and the pad. The NMOS protect circuit is configured to be activated only for a duration of the overshoot voltage received at the pad during the receive mode and the PMOS protect circuit is configured to be activated only for a duration of the undershoot voltage received at the pad during the receive mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.