Group III-N nanowire transistors

US9240410B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Han Wui Then · Portland, US
• Robert S. Chau · Beaverton, US
• Benjamin Chu-Kung · Portland, US
• Gilbert Dewey · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Matthew V. Metz · Portland, US
• Niloy Mukherjee · Beaverton, US
• Ravi Pillarisetty · Portland, US
• Marko Radosavljevic · Portland, US

Key dates

• Filing date: Dec 19, 2011
• Grant date: Jan 19, 2016
• Expiry date: Sep 24, 2032

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/938
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.