Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof
US9240791B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2015 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | May 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17748
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and is configurable to connect with adjacent logic tile. Each logic tile includes a plurality of input/output clock paths, wherein each input/output clock path is associated with a different edge of the logic tile. The plurality of input/output clock paths include a plurality of input clock path, each input clock path configurable to receive a tile input clock signal from an adjacent first logic tile, and a plurality of output clock paths, each output clock path configurable to output a tile output clock signal to an adjacent second logic tile. An output clock path includes a u-turn circuit to receive a tile clock signal having a first predetermined skew and provide a tile clock signal having a second predetermined skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.