Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses
US9244846B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2012 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Feb 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.